Experience in standard IC design methodology with functional simulation and analysis, PPA analysis including design for reliability.
Expert in SystemVerilog and Specman E test-bench language and UVM. Develops scalable and portable test benches.
STD Cell Layout
Analog Mixed Signal Layout
Implementation of analog blocks, resistors, capacitors, pads IOs, ESD structures, etc.
Place and Route
Driven block/chip physical implementation through synthesis, formal verification, floor planning, pin planning, IR drop analysis, sign-off, etc.
Our Track Record
& growing – team of experts
years of combined engineering experience
foundries – exposure
process node handled
Our new-generation workforce
is a growing collective of industry pioneers and fresh minds that altogether raises the strength of our engineering services.